 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| IRDC3710-DF SupIRBuck DESCRIPTION TM USER GUIDE FOR IRDC3710-DF EVALUATION BOARD The IR3710M is single phase sync-buck PWM controller IC optimized for efficiency in high performance portable electronics. The switching modulator uses constant ON-time control. Constant ON-time with diode emulation provides the highest light load efficiency required for all applications. Key features offered by the IR3710M include: programmable switching frequency, soft start, forced continuous conduction mode (FCCM) operation at light load and over current protection. Additional features include pre-bias startup, very precise 0.5V reference, over/under voltage fault protection, power good output, and enable input with voltage monitoring capability. The gate drive is designed to operate up to 7.5V to enhance over all system efficiency. This user guide contains the schematic and bill of materials for the IRDC3710-DF evaluation board. The guide describes operation and use of the evaluation board itself. Detailed specifications and application information for IR3710M is available in the IR3710M data sheet. BOARD FEATURES * Vin = +12V Typical ( 8-19V input Voltage range. See note below) * PVcc= +5.0V * Vcc=+3.3V * Vout = +1.1V @ 0- 24A * Fs = 300kHz @ 24A * L = 0.5uH * Cin= 2x10uF (ceramic 1210) + 1x330uF (electrolytic) * Cout= 2x10uF (ceramic 1206) + 2x330uF(SP Cap) Note: At low input line an additional 10uF ceramic capacitor is recommended at input to handle higher ripple current) 1 IRDC3710-DF CONNECTIONS and OPERATING INSTRUCTIONS A regulated +12V input supply should be connected to VIN+ and Vin-. A maximum 24A load should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IRDC3710-DF has three input connectors, one for gate drive supply (PVcc),one for biasing (Vcc) and the third one as input voltage (Vin). Separate supplies should be applied to these inputs. PVcc input should be a well regulated 4.5V-5.5V supply and it would be connected to +5V and PGND and Vcc input should be a well regulated 3.0V-3.6V supply and it would be connected to +3.3V and AGND. An external signal can be provided as Enable signal to turn on or turn off the converter if desired. This signal is not required to power up the Evaluation board as EN pin is connected to a voltage divider from Vin. The absolute maximum voltage of Enable signal is +3.9V. The evaluation board is configured for use with 2x10uF (ceramic 1206) + 2x330uF (SP) capacitors. However, the design can be modified for an all ceramic output cap configuration by adding the inductor DCR sensing circuit as show in the schematic. Table 1: Connections Connection VIN+ VIN+5V +3.3V PGND AGND VOUT+ VOUT+ Enable Signal Name VIN (+12V) Ground of VIN PVcc input (+5.0V) Vcc input (+3.3V) Ground for PVcc input Ground for Vcc input Vout (+1.1V) Ground of Vout Enable input LAYOUT The PCB is a 4-layer board. All layers are 2 Oz. copper. The IR3710M and other components are mounted on the top and bottom side of the board. Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located close to IR3710M. The feedback resistors are connected to the output voltage at the point of regulation and are located close to IR3710M. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 2 IRDC3710-DF Vin = +12V Vin- V out- Enable Vcc = +3.3V Vout = +1.1V GROUND PVcc = +5.0V GROUND Figure 1: Connection diagram of IRDC3710-DF evaluation board 3 IRDC3710-DF Figure 2: PCB layout, top layer Figure 3: PCB layout, bottom layer 4 IRDC3710-DF Figure 4: Board layout, mid-layer I Figure 5: Board layout, mid-layer II 5 IRDC3710-DF 6 Figure 6: Schematic of the IRDC3710-DF Evaluation board IRDC3710-DF Bill of Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 31 4 1 1 2 1 5 1 2 2 1 4 1 1 1 1 1 1 1 1 3 1 3 1 1 1 1 C1,C2,C3,C4 C5 C7 C8,C9 C10 C11,C15C18,C20,C22 0.1uF 2.2uF 1.0uF 10uF 330uF N/S 1.0uF 330uF 10uF 22000pF N/S BAT54S BAS316 500nH IRF6720S2TRPBF IRF6729MTRPBF 48.7K 180K 4.75k N/S 1.96K 10K 0 1.65K Switch, 2-Pos. IR3710MMPbF Ceramic,25V,0603,X7R,10% Ceramic, 6.3V, 0603, X7R, 10% Ceramic, 25V, 0805, X5R, 10% Ceramic,25V,1210,X5R,10% SMD Elecrolytic, 25V,F-size,20% No Stuff Ceramic,25V,0603,X5R,10% SP-Cap,Dcase,4V,20% Ceramic,6.3V,1206,X5R,20% Ceramic,50V,0603,X7R,10% No Stuff Dual Diode,40V,BAT54S,SOT-23 Phillips 30V , 0.25A SMT-Inductor,0.8mOhms,Toko FDUE1245-R50M IRF6720 30V IRF6729 30V Thick-film,0603,1/10W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% No Stuff Thick-film,0603,1/10W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,5% Thick-film,0603,1/10W,1% Switch, DIP, 2-Pos., SPDT IR3710M, Controller,PQFN,3x3mm C12 C13,C14 C16,C17 C19 C21,C23,C24,C25 D1 D2 L1 Q1 Q2 R4 R5 R7 R9,R11,R16 R12 R13,R17,R18 R14 R15 SW1 U1 7 IRDC3710-DF TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V,Vo=1.1V, Io=0- 24A, , Room Temperature, No Air Flow Ch1-Phase Voltage(10V/Div) Ch3-CPO(2V/Div) Ch2-Vout(50mV/div) Time: 10uS/Div) Ch1-Phase Voltage(10V/Div) Ch3-CPO(2V/Div) Ch2-Vout(50mV/div) Time: 2uS/Div) Figure 7: Charge Pump Off at Iout = 0.5A Figure 8: Charge Pump On at Iout =5A Ch1-Phase Voltage (10V/Div) Ch2-Vout(50mV/Div) Ch1-Phase Voltage (10V/Div) Ch2-Vout(50mV/Div) Figure 9: Load Step (5A to 15A) Transient at 12Vin Figure 10: Load Step (5A to 15A) Transient at 19Vin 8 IRDC3710-DF TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V,Vo=1.1V, Io=0- 24A, Room Temperature, No Air Flow Ch1-Phase Voltage (10V/Div) Ch2-Vout(50mV/Div) Ch1-Phase Voltage (10V/Div) Ch2-Vout(50mV/Div) Figure 11: DCM/CCM transition from 1.0A to 5A at 12Vin Figure 12: DCM/CCM transition from 1.0A to 5A at 19Vin Ch1-Phase Voltage (10V/Div) Ch3-EN(2V/Div) Ch2-Vout(500mV/Div) Ch4-PGood(2V/Div) Ch1-Phase Voltage (10V/Div) Ch3-EN(2V/Div) Ch2-Vout(500mV/Div) Ch4-PGood(2V/Div) Figure 13: Startup/Shutdown 12Vin at 1.0A Figure 14: Startup/Shutdown 12Vin at 5.0A 9 IRDC3710-DF TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V, Vo=1.1V, Io=0- 24A, , Room Temperature, No Air Flow 95 90 85 80 6 5 4 3 75 2 70 65 60 0 4 8 12 Iout(A) Eff 12V Input CP ON Power Loss 12V Input with CP Eff 12V Input No CP Power Loss 12V input No CP 16 20 24 1 0 Figure 15: Typical Efficiency and Power Loss at Vin-12V 95 90 4 85 80 75 70 1 65 60 0 4 8 12 Iout(A) 19V Input CP ON Power Loss 8V Input 8V Input CP ON Power Loss 19V Input 16 20 24 0 3 Power Loss(W) Efficiency(%) 5 2 Figure 16: Typical Efficiency and Power Loss at Vin=8V and 19V Power Los(w) Efficiency(%) 10 IRDC3710-DF TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V, Vo=1.1V, Io=0- 24A, , Room Temperature, No Air Flow 1.105 1.103 1.101 1.099 Vout(V) 1.097 1.095 1.093 1.091 1.089 1.087 1.085 0 4 8 12 Iout(A) 16 20 24 12V input 8V Input 19V Input Figure 17: Typical Output Voltage Regulation Q1: 73.0C, Q2:77.3C, Inductor: 51.6C, PCB: 52.8C Figure 18:Thermal Image @12Vin, 24A, With CP On 11 IRDC3710-DF TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V, Vo=1.1V, Io=0- 24A, , Room Temperature, No Air Flow Q1: 77.7C, Q2:82.4C,Inductor: 53.3C, PCB: 54.1C Figure 19: Thermal Image @19Vin, 24A, With CP On Q1:81C,Q2:83.6C, Inductor: 53.1C, PCB: 53.6C Figure 20: Thermal Image @12Vin, 24A, With CP Off 12 IRDC3710-DF PACKAGE INFORMATION 13 |
Price & Availability of IRDC3710-DF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |